CoWoS Token Economics

TSMC's advanced-packaging expansion is one of the more measurable pieces of the AI capital-expenditure cycle. A July 2026 Fubon Research model projects 1.16 million TSMC CoWoS wafers in 2026 and 1.89 million in 2027, an increase of 64%. NVIDIA is expected to retain about half the allocation, even as custom-ASIC suppliers gain share.

That is the supply story. The investment story has another denominator: revenue earned per useful token, per dollar of deployed capital and per watt of available power. More packaging can increase accelerator shipments while reducing scarcity rents, especially if inference software improves and cloud rental rates compress. The likely winners depend on which constraint remains binding.

My framework separates three bets: TSMC and packaging vendors sell scarce manufacturing capacity; NVIDIA, AMD and ASIC designers sell compute systems; hyperscalers buy those systems and must monetize their output. The economics differ sharply.

1. Who gets the packaging?

The table is Fubon's forecast of annual TSMC CoWoS shipments, in thousands of 300 mm packaging wafers. These are analyst estimates rather than disclosed purchase orders. The final column is my illustration, not a forecast: 2.4 million wafers in 2028, with the 2027 customer mix held constant.

Source: Fubon Research, July 28, 2026, Figure 5. The 2028 total assumes average production of 200,000 wafers/month, consistent with an illustrative ramp from 180,000/month at end-2027 to 220,000/month at end-2028. Individual 2028 allocations are not publicly established.

Two conclusions are more robust than the apparent precision of the numbers.

NVIDIA's share is not collapsing. Its projected allocation grows 61% in 2027 while remaining approximately half of TSMC's CoWoS output. Custom silicon is growing alongside NVIDIA, not demonstrably replacing it. The real risk to NVIDIA is not simply fewer units; it is whether system pricing and gross margin can withstand better competing inference economics and higher memory costs.

The custom-ASIC channel is growing faster. Broadcom and MediaTek together rise from 280,500 wafers to 559,500—almost doubling in a year. Google is economically exposed to this channel through TPU design partnerships, but there is no separate Google row. Broadcom also serves customers other than Google. Adding GOOG on top of these rows would double-count the same packaging supply. Moreover, the forecast includes some non-accelerator products: a CoWoS wafer is not synonymous with a finished AI GPU.

Fubon's larger NVIDIA and AMD “total allocation” figures include other packaging providers, such as SPIL and ASE, so they should not be substituted into this TSMC-only table. The scope difference matters especially for AMD. Fubon, pp. 1 and 4.

2. Which stocks actually capture the value?

TSM is the clearest bottleneck exposure, not automatically the best-valued stock. Its economics benefit from serving NVIDIA and ASIC competitors simultaneously; its investment cost rises with the ramp. TSMC projected $60–64 billion of total 2026 capital expenditure, which is company-wide, not exclusively CoWoS. The underwriting question is how long higher utilization and advanced-node mix outrun depreciation and margin dilution. TSMC Q3 2026 earnings transcript.

NVDA owns the largest manufacturing reservation but not necessarily the best incremental token economics. A strong position in packaging is evidence of supply access and expected demand; it is not evidence of chip gross margin, realized rental prices or end-customer returns. NVIDIA's defensibility increasingly rests on the full rack, software and interconnect—not peak floating-point throughput alone.

AVGO is a way to own custom silicon without betting on one cloud operator's utilization. The opportunity is substantial, but the customer owns the architecture and may capture much of the cost advantage. In evaluating AVGO, the relevant variable is design and networking profit earned as custom accelerator deployments convert to revenue, not an assumption that every Broadcom-allocated wafer is a Google TPU.

AMD has more operating leverage from a smaller starting base. Its TSMC allocation is roughly one-seventh of NVIDIA's in 2027, but published benchmarks show it can be competitive on the right inference workload. Revenue realization, software progress and margins are more useful to underwrite than treating a 6 GW customer announcement as an immediate sale.

3. The price of compute is becoming the more important signal

Peak compute is a poor proxy for what a cloud buyer can sell. For hardware comparison, the figures below use dense BF16 rather than the larger sparse-operation marketing figures.

Sources: NVIDIA Blackwell Ultra datasheet and AMD accelerator specifications. GPU power is nameplate/configured power, not measured rack electricity consumption.

For a common serving workload, MLPerf Inference v6.1, GPT-OSS-120B, Server scenario, the eight-GPU results correspond to approximately 11,276 output tokens/s per B200, 13,777 per B300, and 14,155 per MI355X after dividing system throughput by eight. These are system-level, latency-constrained benchmark results, not single-user speed or a guarantee that every cloud image reproduces them. NVIDIA inference results, Dell B300 submission, AMD MI355X submission.

Now anchor those results against published rental offers, rather than theoretical chip purchase prices.

Rental sources: DeepInfra, Nebius, TensorWave and Oracle. TensorWave's starting rate has unspecified qualifying terms; it is not necessarily an on-demand offer. The rated-kW column normalizes compute rental, not the price of electricity.

The last column is simply:

Rental cost per million output tokens = (GPU-hour rental × 1,000,000) / (3,600 × benchmark output tokens/s/GPU).

It assumes a continuously productive rental and comparable optimized serving stacks. At 80% productive utilization, multiply by 1.25. Storage, network, CPU, power overhead, platform operations and customer acquisition are excluded. These are infrastructure cost floors, not public API selling prices, which must also pay for prefill, orchestration, model development and profit.

The wide spread between public cloud rates is itself an investment signal: peak token throughput does not automatically translate into pricing power. A chip can be fast and still yield weak returns if demand or rental realizations are low. Conversely, an apparently expensive chip can be the cheapest way to meet a latency or model-quality requirement. Google Ironwood and AWS Trainium belong in this competitive set, but public rental rates on different models and workloads do not establish a valid apples-to-apples GPT-OSS token-cost ranking.

Ownership versus rental

Whole-server retail anchors help bound the economics. Published eight-GPU B200 systems span roughly $446,000–$550,000 and B300 systems roughly $554,000–$786,000, depending on configuration. At four-year straight-line depreciation and 80% productive hours, that is $1.99–$2.45 per B200 productive GPU-hour and $2.47–$3.50 per B300 productive GPU-hour, capital cost alone. That compares with the rental rates above but excludes financing, electricity, racks, networking, maintenance and data-center overhead. These are OEM server quotes, not disclosed hyperscaler acquisition prices. Supermicro systems; Lenovo total-cost study, June 2026.

4. How many watts and tokens do booked wafers imply?

The useful way to translate packaging into compute is a sensitivity, not a shipment forecast:

Good chip equivalents = packaged wafers × packages per wafer × packaging yield.

Full-year output-token run rate = chip equivalents × tested output tokens/s/chip × 31,536,000 seconds × productive-utilization fraction.

For a transparent illustration, assume every NVIDIA wafer produces 14 good B300-equivalent packages and every AMD wafer 11.04 good MI355X-equivalent packages—design-specific historical packaging proxies—and assume 80% productive inference use for a full year. These intentionally constant products are not the expected 2027–28 SKU mix.

Arithmetic only, derived from the Fubon wafer estimates, illustrative Epoch AI packaging methodology, and the GPT-OSS benchmark above. GW is rated accelerator wattage, not measured electricity draw, grid connection, rack power or incremental power demand. “Run rate” assumes the entire cohort is deployed for a full year; output produced during each manufacturing year would be substantially lower.

This calculation is useful precisely because its limitations are visible. Rubin has a different interposer footprint from B300; future AMD packages differ from MI355X; not every allocated wafer goes into the chosen reference accelerator; some chips train rather than serve; installation is staggered; and enough paid inference demand may not exist to fill the fleet. Fubon's actual NVIDIA 2027 chip-output estimate is 12.4 million, for example, versus the 13.2 million B300 equivalents in this mechanical calculation. The gap illustrates why wafers × one fixed GPU yield cannot be treated as a shipment forecast.

The real utilization question is not “is the GPU busy?” It is what fraction of purchased capacity is delivering billable, latency-compliant work. GPU busy-time percentages, model FLOPs utilization during training, scheduled occupancy and inference goodput are different metrics. An assumed 80% service occupancy is not an observed NVIDIA, Google or AMD fleet statistic. Applying a training MFU discount again to an already-measured inference benchmark would double-count inefficiency.

5. The demand is real; the purchase prices are not public

Several deals substantiate a multi-year demand pipeline without resolving the return-on-capital question:

Sources: AMD–Meta, OpenAI–AMD, OpenAI–Broadcom. Multi-year GW agreements are neither 2027 installed power nor additive to the TSMC wafer table. In particular, no buyer-specific chip $/W or $/token contract price is available publicly.

These agreements improve confidence that customers intend to build, but they do not tell us what investors most need: how much incremental gross profit buyers earn on that installed base. For hyperscalers, the critical comparison is the growth in monetized AI workloads against depreciation and capital spending. For suppliers, it is gross margin sustained through the transition to higher bandwidth memory, larger packages and competing accelerators.

6. The underwriting checklist for 2027–28

The most useful quarterly observations are:

1. Capacity to revenue: TSMC's actual advanced-packaging throughput, yield and pricing—not just announced monthly capacity. Track alternative packaging capacity from ASE, Amkor and others because relieving the bottleneck may shift negotiating leverage.
2. Chip mix and costs: NVIDIA Blackwell-to-Rubin and AMD MI355X-to-MI400-class ramp, especially package area, HBM cost and network/rack content. More wafers need not mean proportionally more GPUs.
3. Cloud clearing price: identical-GPU rental quotes, commitments versus on-demand pricing, and realized utilization. A falling GPU-hour price with rising GPU count can mean either healthy efficiency gains or eroding scarcity rents.
4. Economic goodput: output tokens per wall joule at fixed model quality and latency, followed by dollars of revenue and gross profit per installed watt. BF16 FLOP/s/W is only a hardware ceiling.
5. Customer return: AI service revenue, operating cash flow after capital expenditure, and depreciation assumptions. GW of commitments cannot substitute for a customer P&L.

Bull case: CoWoS and HBM stay constrained, demand absorbs rising supply, new generations increase useful tokens per MW, and enough of that saving is retained by suppliers in price and margin. TSMC captures fabrication and packaging volume; NVIDIA and ASIC designers capture rising compute-system budgets; cloud operators monetize the lower unit costs.

Bear case: Packaging bottlenecks clear faster than paid demand grows. Competitive hardware and software reduce the market-clearing GPU-hour price; chips depreciate economically before accounting depreciation ends; buyers benefit from lower costs while suppliers suffer price or margin compression. The same growth in wafer shipments can then coincide with much worse stock returns.

The key distinction is capacity growth versus economic scarcity. The 2026–27 wafer expansion is supported by a specific analyst model. The 2028 company split, chip equivalents and quintillion-token numbers are scenarios. None establishes what the market should pay today for TSM, NVDA, AVGO, AMD or the hyperscalers. That requires a separate valuation against earnings, reinvestment and the price already embedded in each stock.

Related: AI Supply Chain, an interactive map of the listed suppliers, buyers and gross-margin relationships.